HW-USBN-2A Lattice Emulator ISP Download Cable JTAG Programmer for FPGA CPLD

3800.00 {Inc. GST}

GST Input Tax Credit is available

Dispatch Time 12 to 15 days

SKU: OMP-PR144 Category:

Description

Based on the provided product specification and pin link description, here’s a summary of the key features and components of the Lattice USB download line:

Product Specification:

  1. Design Quality Guarantee: Original design solution quality guarantee ensuring compatibility stability.
  2. Driver Installation Not Required: Direct support for Diamond/ispLever6.x/7.x/classic version, ispVM various versions.
  3. FPGA Support: Supports Lattice full range of FPGAs including SC/SCM/XP/XP2/EC/ECP2/ECP2M/MachXO/MachXO2 series.
  4. CPLD Support: Supports Lattice full range of CPLDs such as 1000/2000/4000 series.
  5. USB Interface: Standard USB interface using a standard USB cable to connect to a PC.
  6. USB Powered: USB power supply, no external power supply required.
  7. Compatibility: Interface power from the target board to ensure strong compatibility.
  8. Programming Modes: Supports JTAG, internal FLASH, SPI FLASH, and other programming modes.
  9. Operating System Support: Compatible with WIN 2K, WIN XP, WIN7 32, WIN7 64, and other operating systems.
  10. Development Environment Support: Supports LSC ISPVM, LATTICE DEMIOND, LATTICE ISPEVER, and LATTICE PROGRAMMER development environments.

Pin Link Description:

  1. SCLK/TCK: Connected to the chip’s SCLK/TCK pin.
  2. GND: Common ground of downloader and target board connected to pins 2 and 4.
  3. MODE/TMS: Connected to the MODE/TMS pin of the chip.
  4. SDI/TDI: Connected to the chip’s SDI/TDI pin.
  5. VCC: Used to detect if the target board is powered on, not to power the target board itself.
  6. SDO/TDO: Connected to the chip’s SDO/TDO pin.
  7. INTI, TRST, PROG/ispEN: Need to connect these pins for downloading and debugging certain chips, not every chip needs these connections.

Shipping List:

  1. Lattice USB download line body.
  2. USB 2.0 high-speed link line.
  3. 10-pin 2.54MM pitch JTAG connection.
  4. 10 with a single share of DuPont.

This comprehensive package includes everything needed for programming and debugging Lattice FPGAs and CPLDs.

Additional information

Weight 250 g

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